Digital integration
Purely digital elements provide the intended implementation basis for both ASIC and FPGA targets.
THE TECHNOLOGY
From physical behaviour
to a digital interface.
Phystech TRNG explores a hardware entropy architecture built with digital logic. Its published patent documents describe an autonomous Boolean network and a sampling arrangement for a synchronous output.
Public architectural description
An autonomous Boolean network.
The patent describes interconnected logic elements operating without a clock inside the source network. The evolving signal is sampled to form a synchronous output. This conceptual distinction between the source and its output interface matters when discussing integration.
EP3926462B101
Source network
Autonomous behaviour in interconnected logic.
02
Signal sampling
Capture the source signal at the output boundary.
03
Synchronous output
Provide values to the surrounding digital system.
This simplified view explains the source-to-interface relationship. It is not a netlist, an implementation specification or a depiction of the complete security subsystem.
DESIGNED AROUND THE SYSTEM
One source. A full operating cycle.
Phystech’s stated design combines a purely digital implementation with continuity across startup, reboot and energy-saving operation.
- 01Power on
- 02Generate
- 03Sleep / wake
- 04Restart
Ready without warm-up
The stated behaviour covers initial startup and reboot without a warm-up period.
Fit the system budget
Small footprint, low power and high generation speed are joint design priorities.
Scale across devices
The intended scope extends from compute platforms to resource-constrained microcontrollers.
These are developer-stated characteristics. Implementation-specific limits and supporting measurements will be added to the project materials.
SEMICONDUCTOR IP
A building block for your chip.
The intended delivery is an integration-ready IP Core: an implementation an engineering team can assess and incorporate into a semiconductor design.
Implementation & interfaces
An RTL / HDL implementation or another suitable representation, with interface specifications and configuration options.
Verification & integration
Testbenches, verification results, implementation constraints and guidance for the target design flow.
Characterization & assurance
Entropy assessment, power, performance and area measurements, operating limits and security documentation for the specific implementation.
This is the intended product scope, not an inventory of deliverables available today. The exact implementation format and package contents remain to be confirmed.
The integration discussion starts with the hardware platform and its constraints, rather than a particular CPU instruction set.
TECHNICAL EVALUATION
Entropy quality.
Implementation characteristics.
A useful comparison identifies the implementation, the system boundary and the conditions behind every result.
- Entropy & output rate
- Min-entropy per raw sample; raw, conditioned and delivered output rates; conditioning assumptions.
- Power & area
- Energy per entropy bit, active and standby power, area or gate count, including support logic.
- Operating range
- Voltage, temperature and process conditions; variation between instances; relevant fault and environmental tests.
- Startup & monitoring
- Time to usable output after startup, reboot and wake; startup and continuous health tests; failure response.
- Implementation & portability
- Platform, process and constraints; what changes in a port and which measurements must be repeated.
- Reproducible evidence
- Data collection method, implementation version, comparison baseline, report authors and independent assessment.
Assessment references
SP 800-90B addresses entropy sources; SP 800-90C addresses complete random-bit-generator constructions. These references guide evaluation questions, not a claim of Phystech certification.