EP3926462B1
European patent publication describing the Boolean-network architecture and its synchronous output arrangement.
- Publication date
PUBLIC MATERIALS
Public patent documents describe the architecture. Each entry identifies the document type and source.
European patent publication describing the Boolean-network architecture and its synchronous output arrangement.
US patent publication providing the description, figures and claims of the invention.
A later US application publication. This document is identified as an application publication, not as a granted patent.
The intended product is an integration-ready semiconductor IP Core. The public evidence below shows what can be reviewed today.
Published architecture and patent documents describing the invention.
Published materialsView evidence ↗A working implementation with measurements, test conditions and, where available, independent assessment.
Not yet documented on this siteAn implementation package with interfaces, constraints, documentation and a verification environment.
Not yet documented on this siteCharacterization of the final implementation. Prototype results do not automatically transfer to another platform or process.
Not yet documented on this sitePublication status is shown here; it does not establish the internal development stage. Prototype, implementation and independent-validation status remain to be confirmed with the technical team.
TECHNICAL EVALUATION
A useful comparison identifies the implementation, the system boundary and the conditions behind every result.
SP 800-90B addresses entropy sources; SP 800-90C addresses complete random-bit-generator constructions. These references guide evaluation questions, not a claim of Phystech certification.