Operating conditions
Voltage, temperature, process variation and restarts must be included in the assessment.
Hardware True Random Number Generator
Physical entropy.
For secure silicon.
A hardware true random number generator based on a patented digital architecture, being developed as semiconductor IP for security engines and hardware roots of trust.
A project by Phystech Technologies Lab
01Boolean network
02Signal sampling
03Digital output
A simplified view of the approach described in the patent. Not a circuit diagram.
SEMICONDUCTOR IP
The essentials, at a glance.
- Architecture
- An autonomous Boolean-network entropy source with a synchronous digital output.
- Intended product
- A semiconductor IP Core for SoCs, embedded devices and hardware security.
- Evidence today
- Public patent descriptions. Implementation metrics and independent reports are not yet published on this site.
01 / ENGINEERING CHALLENGES
Entropy must hold up
in the target system.
The difficult part is making a physical entropy source dependable and practical throughout the life of a chip.
Evidence for validation
A test suite alone is not an entropy model, a health-testing strategy or formal validation.
Portability & integration
A new platform or process can change physical behaviour and the implementation constraints.
Power, performance & area
Area, energy and usable entropy throughput compete for the same system budget.
Assessment context: NIST SP 800-90B · NIST SP 800-90C
02 / APPLICATIONS & MARKETS
Entropy for
hardware security.
A hardware entropy source supports key generation and other cryptographic tasks in processors, embedded devices and security hardware.
Compute & platform security
Entropy for key generation and SoC security functions.
Phystech’s digital architecture targets integration into chip designs, with an IP package intended to support reuse across product families.GLOBAL MARKET SCALE
- Smartphones shipped
- 1.3 billion2025 · Annual shipmentsIDC — Smartphones shipped, 2025 · Annual shipments
- PCs shipped
- 284.7 million2025 · Annual shipmentsIDC — PCs shipped, 2025 · Annual shipments
- Logic semiconductor sales
- $301.9 billion2025 · Annual marketSIA / WSTS — Logic semiconductor sales, 2025 · Annual market
Smartphones and PCs illustrate the scale of processor platforms. The logic figure covers a broader chip category, not just CPUs or security functions.
Embedded & industrial
Randomness for secure communication and on-device key generation.
The design targets a small footprint and low power, with consistent behaviour across sleep and wake cycles for devices with limited resources.GLOBAL MARKET SCALE
- Connected IoT devices
- 21.1 billionEnd of 2025 · Installed baseIoT Analytics — Connected IoT devices, End of 2025 · Installed base
- Enterprise IoT spending
- $324.0 billion2025 · Annual marketIoT Analytics — Enterprise IoT spending, 2025 · Annual market
- Connected IoT devices
- 39.0 billion2030 · Installed-base forecastIoT Analytics — Connected IoT devices, 2030 · Installed-base forecast
Device counts cover consumer and enterprise IoT; spending covers enterprise IoT. Neither figure is MCU shipments or security-only demand.
Dedicated security
Fresh entropy for key generation and other cryptographic operations.
The architecture targets high generation speed and stable startup and reboot behaviour for the cryptographic subsystem.GLOBAL MARKET SCALE
- eSIM units shipped
- 605.0 million2025 · Annual shipment estimateTCA — eSIM units shipped, 2025 · Annual shipment estimate
- Hardware security modules
- $1.8 billion2025 · Annual market estimateGrand View Research — Hardware security modules, 2025 · Annual market estimate
- Hardware security modules
- $5.0 billion2033 · Annual market forecastGrand View Research — Hardware security modules, 2033 · Annual market forecast
eSIM shipments illustrate one secure-element application. The HSM market is a separate category including on-premise and cloud deployments.
The benefits described are design objectives. Suitability and performance are evaluated for each implementation.
These figures describe application markets, not Phystech’s addressable share. Shipments, installed devices and market spending have different scopes. The segments overlap and are not additive. All monetary figures are in US dollars; projections are marked as forecasts. Figures are rounded to one decimal place.
POTENTIAL APPLICATION ECOSYSTEMS
From chip design to cloud infrastructure.
The intended digital TRNG IP core could serve both chip and device manufacturers and semiconductor IP providers. These examples show where the technology may be relevant, subject to confirmation of its characteristics.
AI, GPU & high-performance computing
An entropy source for key generation and hardware roots of trust in GPU, DPU and AI accelerators, including confidential computing platforms.
Mobile devices & custom SoCs
Local entropy for secure enclaves, device authentication and cryptographic keys in mobile SoCs, where chip area and power budgets matter.
Cloud & hyperscale infrastructure
Hardware entropy within cloud HSMs, secure servers and custom processors for key generation and confidential computing.
Semiconductor IP & chip design
The intended TRNG IP core could complement security IP portfolios and design flows for integration into ASIC, FPGA, SoC and MCU platforms.
Chip manufacturers & foundries
A digital entropy architecture for new secure chips and platforms, with integration and validation for each target process.
MCUs, secure elements & embedded systems
On-device key generation and secure identity for IoT, industrial and automotive electronics, including operation across sleep and restart cycles.
Secure computing, identity & cryptographic hardware
A hardware entropy source for HSMs, secure elements, TPMs, tokens and payment devices supporting keys and digital identity.
Industrial & critical systems
Local entropy for authenticated controllers, secure communications and edge devices in automation, critical infrastructure and automotive systems.
Potential integration platforms and applications
- ASIC
- FPGA
- SoC
- MCU
- CPU
- GPU
- DPU
- Secure Elements
- HSM
- IoT
- Automotive
- Cloud Infrastructure
- Industrial Systems
Company names and logos are examples of organizations and technology ecosystems for which this technology may be relevant based on their publicly known activities. Inclusion does not imply partnership, interest, endorsement or commercial relationships.
03 / ALTERNATIVE SOLUTIONS
Existing approaches.
Engineering tradeoffs.
Hardware systems obtain randomness in different ways. Phystech’s autonomous Boolean-network architecture targets a compact digital source with stable startup behaviour and high generation speed.
Oscillator-based TRNG
Obtains entropy from timing variation in oscillator signals.
Integration tradeoff
Entropy estimation depends on the sampling scheme and physical behaviour. Coupling, voltage and temperature are part of the assessment.
Phystech’s intended contribution
The Boolean-network architecture targets a compact implementation and stable startup without source warm-up. Robustness across voltage and temperature remains to be demonstrated.
Analog or mixed-signal noise source
Captures physical noise and converts it into digital values.
Integration tradeoff
The analog path and conversion add implementation and characterization requirements alongside the digital interface.
Phystech’s intended contribution
A source built from digital elements targets integration without a dedicated analog front end; compactness and power are design priorities.
Entropy source + DRBG
Seeds a deterministic generator from a physical source to produce a fast output stream.
Integration tradeoff
High DRBG output speed does not measure fresh physical-entropy throughput. Source readiness, reseeding and monitoring remain system requirements.
Phystech’s intended contribution
High source generation speed and no source warm-up are stated priorities. Fresh-entropy throughput must be measured separately from any expanded output.
The DRBG is a complementary system component. It may also be used with Phystech. These are implementation tradeoffs and intended contributions, not demonstrated comparative advantages; both architectures require entropy assessment and health testing.
04 / THE PHYSTECH APPROACH
Physical behaviour.
Digital building blocks.
The published architecture uses an autonomous Boolean network as an entropy source, with sampling for a synchronous output. The development objective is an integration-ready IP Core built around this approach.
Explore the architectureThe intended product is an integration-ready IP Core. Interfaces, verification materials and target characterization are part of the development objective.
01
Source
Autonomous Boolean network
02
Sampling
Capture the evolving signal
03
Output
Synchronous digital interface
A simplified view of the approach described in the patent. Not a circuit diagram.
05 / SYSTEM VALUE
Security and integration.
Within the chip’s budget.
Phystech targets an entropy source that combines stable operation, digital integration and efficient use of power and silicon area.
Security assurance
An entropy model, health tests and operating-range measurements form the basis for assessing the source. Implementation validation remains to be documented.
Integration & reuse
The intended IP package combines an implementation, interfaces and verification materials to support integration across product families. Process portability remains to be demonstrated.
Power, speed & area
A small footprint and low power are design priorities for constrained devices. Useful throughput is defined by entropy quality as well as output rate.
Potential benefits to evaluate; quantified savings and comparative advantages require measurements.
06 / PUBLIC EVIDENCE
A clear basis for evaluation.
The architecture is described in public patent documents. Implementation performance, portability and independent validation require separate supporting evidence.
- 01
Technology IP
Published materialsView evidence ↗ - 02
Measured prototype
Not yet documented on this site - 03
Integration-ready IP Core
Not yet documented on this site - 04
Target implementation validation
Not yet documented on this site
European patent publicationEN
EP3926462B1
Read source document — True random number generator, EP3926462B1US patent publicationEN
US12367013B2
Read source document — True random number generator, US12367013B2US application publicationEN
US20250348282A1
Read source document — True random number generator, US20250348282A107 / THE DEVELOPER
Developed by
Phystech Technologies Lab.
A research and engineering team working on hardware security, embedded systems and other technology projects. Phystech TRNG brings the focus to one of those projects.
Explore the lab and its work